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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. february 1996 copyright ? intel corporation, 1996 order number: 271116-005 M87C196KC/m87c196kd 16-bit high-performance chmos microcontrollers with on-chip eprom special environment M87C196KCe16 kbytes eprom, 512 bytes ram m87c196kde32 kbytes eprom, 1024 bytes ram y M87C196KC: 16 mhz operation y m87c196kd: 16 and 20 mhz operation y register-to-register architecture y 28 interrupt sources/16 vectors y peripheral transaction server y 1.4 m s 16 x 16 multiply (20 mhz) y 1.75 m s 16 x 16 multiply (16 mhz) y 2.4 m s 32/16 divide (20 mhz) y 3.0 m s 32/16 divide (16 mhz) y powerdown and idle modes y five 8-bit i/o ports y 16-bit watchdog timer y available in 68-lead pga and 68-lead ceramic quad flatpack packages y dynamically configurable 8-bit or 16-bit buswidth y full duplex serial port y high speed i/o subsystem y 16-bit timer y 16-bit up/down counter with capture y 3 pulse-width-modulated outputs y four 16-bit software timers y 8- or 10-bit a/d converter with sample/hold y hold /hlda bus protocol y product grades e se1 (qml): b 55 cto a 125 c e se2 (qml): b 40 cto a 125 c (m87c196kd only) the M87C196KC/kd 16-bit microcontroller is a high performance member of the mcs -96 microcontroller family. the M87C196KC/kd is an enhanced m80c196kb device with on-chip ram and eprom. intel's chmos iii-e process provides a high performance processor along with low power consumption. four high-speed capture inputs are provided to record times when events occur. six high-speed outputs are available for pulse or waveform generation. the high-speed output can also generate four software timers or start an a/d conversion. events can be based on the timer or up/down counter. for bus design information, configuration, and programming, please see the 8xc196kc/8xc196kd user's manual (order y 272238). mcs -96 is a registered trademark of intel corporation.
M87C196KC/m87c196kd 271116 1 figure 1. M87C196KC/kd block diagram packaging pga cqfp signal 1 9 ach7/p0.7 2 8 ach6/p0.6 3 7 ach2/p0.2 4 6 ach0/p0.0 5 5 ach1/p0.1 6 4 ach3/p0.3 7 3 nmi 82ea 91v cc 10 68 v ss 11 67 xtal1 12 66 xtal2 13 65 clkout 14 64 buswidth 15 63 inst 16 62 ale/adv 17 61 rd 18 60 ad0/p3.0 19 59 ad1/p3.1 20 58 ad2/p3.2 21 57 ad3/p3.3 22 56 ad4/p3.4 23 55 ad5/p3.5 pga cqfp signal 24 54 ad6/p3.6 25 53 ad7/p3.7 26 52 ad8/p4.0 27 51 ad9/p4.1 28 50 ad10/p4.2 29 49 ad11/p4.3 30 48 ad12/p4.4 31 47 ad13/p4.5 32 46 ad14/p4.6 33 45 ad15/p4.7 34 44 t2clk/p2.3 35 43 ready 36 42 t2rst/p2.4/ainc 37 41 bhe /wrh 38 40 wr /wrl 39 39 pwm0/p2.5 40 38 t2capture/p2.7/pact 41 37 v pp 42 36 v ss 43 35 hs0.3 44 34 hs0.2 45 33 t2up-dn/p2.6 46 32 p1.7/hold pga cqfp signal 47 31 p1.6/hlda 48 30 p1.5/breq 49 29 hso.1 50 28 hso.0 51 27 hso.5/hsi.3 52 26 hso.4/hsi.2 53 25 hsi.1 54 24 hsi.0 55 23 p1.4/pwm2 56 22 p1.3/pwm1 57 21 p1.2 58 20 p1.1 59 19 p1.0 60 18 txd/p2.0 61 17 rxd/p2.1 62 16 reset 63 15 extint/p2.2 64 14 v ss 65 13 v ref 66 12 angnd 67 11 ach4/p0.4 68 10 ach5/p0.5 figure 2. pin definitions 2
M87C196KC/m87c196kd packaging the M87C196KC/kd is available in a ceramic pin grid array, shown in figure 3, and a leaded ceramic quad pack shown in figure 4. 271116 33 figure 3. 68-pin grid array pinout 3
M87C196KC/m87c196kd 271116 2 figure 4. 68-pin ceramic quad flatpack 4
M87C196KC/m87c196kd pin descriptions symbol name and function v cc main supply voltage (5v). v ss digital circuit ground (0v). there are three v ss pins, all of which must be connected. v ref reference voltage for the a/d converter (5v). v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. must be connected for a/d and port 0 to function. angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . v pp timing pin for the return from powerdown circuit. connect this pin with a 1 m f capacitor to v ss anda1m x resistor to v cc . if this function is not used v pp may be tied to v cc . this pin is the programming voltage on the eprom device. xtal1 input of the oscillator inverter and of the internal clock generator. xtal2 output of the oscillator inverter. clkout output of the internal clock generator. the frequency of clkout is (/2 the oscillator frequency. reset reset input to the chip. buswidth input for buswidth selection. if ccr bit 1 is a one, this pin selects the bus width for the bus cycle in progress. if buswidth is a 1, a 16-bit bus cycle occurs. if buswidth i sa0an 8-bit cycle occurs. if ccr bit 1 is a 0, the bus is always an 8-bit bus. nmi a positive transition causes a vector through 203eh. inst output high during an external memory read indicates the read is an instruction fetch. inst is valid throughout the bus cycle. inst is activated only during external memory accesses and output low for a data fetch. ea input for memory select (external access). ea equal to a ttl-high causes memory accesses to locations 2000h through 5fffh to be directed to on-chip eprom. ea equal to a ttl-low causes accesses to those locations to be directed to off-chip memory. ale/adv address latch enable or address valid output, as selected by ccr. both pin options provide a signal to demultiplex the address from the address/data bus. when the pin is adv , it goes inactive high at the end of the bus cycle. ale/adv is activated only during external memory accesses. rd read signal output to external memory. rd is activated only during external memory reads. wr /wrl write and write low output to external memory, as selected by the ccr. wr will go low for every external write, while wrl will go low only for external writes where an even byte is being written. wr /wrl is activated only during external memory writes. bhe /wrh bus high enable or write high output to external memory, as selected by the ccr. bhe e 0 selects the bank of memory that is connected to the high byte of the data bus. a0 e 0 selects the bank of memory that is connected to the low byte of the data bus. thus accesses to a 16-bit wide memory can be to the low byte only (a0 e 0, bhe e 1), to the high byte only (a0 e 1, bhe e 0), or both bytes (a0 e 0, bhe e 0). if the wrh function is selected, the pin will go low if the bus cycle is writing to an odd memory location. bhe /wrh is valid only during 16-bit external memory write cycles. 5
M87C196KC/m87c196kd pin descriptions (continued) symbol name and function ready ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. when the external memory is not being used, ready has no effect. hsi inputs to high speed input unit. four hsi pins are available: hsi.0, hsi.1, hsi.2 and hsi.3. two of them (hsi.2 and hsi.3) are shared with the hso unit. hso outputs from high speed output unit. six hso pins are available: hso.0, hso.1, hso.2, hsi.3, hso.4 and hso.5. two of them (hso.4 and hso.5) are shared with the hsi unit. port 0 8-bit high impedance input-only port. these pins can be used as digital inputs and/or as analog inputs to the on-chip a/d converter. port 1 8-bit quasi-bidirectional i/o port. port 2 8-bit multi-functional port. all of its pins are shared with other functions in the M87C196KC. ports 3 and 4 8-bit bidirectional i/o ports with open drain outputs. these pins are shared with the multiplexed address/data bus which has strong internal pullups. hold bus hold input requesting control of the bus. hlda bus hold acknowledge output indicating release of the bus. breq bus request output activated when the bus controller has a pending external memory cycle. 6
M87C196KC/m87c196kd electrical characteristics absolute maximum ratings * case temperature under bias b 55 cto a 125 c storage temperature b 65 cto a 150 c voltage on any pin to v ss b 0.5v to a 7.0v power dissipation1.5w notice: this data sheet contains preliminary infor- mation on new products in production. the specifica- tions are subject to change without notice. verify with your local intel sales office that you have the latest data sheet before finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol description min max units t c (se1) case temperature (instant on) b 55 a 125 c t c (se2) case temperature (instant on) b 40 a 125 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v f osc oscillator frequency 3.5 16 mhz f osc oscillator frequency (m87c196kd-20 only) 3.5 20 mhz note: angnd and v ss should be nominally at the same potential. dc characteristics (over specified operating conditions) symbol description min max units test conditions v il input low voltage b 0.5 0.8 v v ih input high voltage (note 1) 0.2 v cc a 1.0 v cc v v ih1 input high voltage on xtal 1, ea 0.7 v cc v cc v v ih2 input high voltage on reset 2.32 v cc v v ol output low voltage 0.3 v i ol e 200 m a 0.45 v i ol e 2.8 ma 1.5 v i ol e 7ma v ol1 output low voltage 0.8 v i ol ea 0.4 ma in reset on p2.5 (note 2) notes: 1. all pins except reset, xtal1 and ea. 2. violating these specifications in reset may cause the part to enter test modes. 7
M87C196KC/m87c196kd dc characteristics (over specified operating conditions) (continued) symbol description min max units test conditions v oh output high voltage v cc b 0.3 v i oh eb 200 m a (standard outputs) v cc b 0.7 v i oh eb 3.2 ma v cc b 1.5 v i oh eb 7ma v oh1 output high voltage v cc b 0.3 v i oh eb 10 m a (quasi-bidirectional outputs) v cc b 0.7 v i oh eb 30 m a v cc b 1.5 v i oh eb 60 m a v oh2 output high voltage 2.0 v i oh eb 0.8 ma in reset on p2.0 (note 7) i li input leakage current (std. inputs) g 10 m a0 k v in k v cc b 0.3v i li1 input leakage current (port 0) g 3 m a0 k v in k v ref i tl 1 to 0 transition current (qbd pins) b 650 m av in e 2.0v i il logical 0 input current (qbd pins) b 70 m av in e 0.45v i ih logical 1 input current (nmi pin) 250 m av in e v cc b 0.3v i cc active mode current in reset 75 ma xtal1 e 16 mhz 93 ma xtal1 e 20 mhz i ref a/d converter reference current 5 ma v cc e v pp e v ref e 5.5v i idle idle mode current 30 ma i pd powerdown mode current 70 m av cc e v pp e v ref e 5.5v r rst reset pullup resistor 6k 65k x v cc e 5.5v, v in e 4.0v c s pin capacitance (any pin to v ss )10pf notes: (notes apply to all specifications) 1. qbd (quasi-bidirectional) pins include port 1, p2.6 and p2.7. 2. standard outputs include ad0 15, rd ,wr , ale, bhe , inst, hso pins, pwm/p2.5, clkout, reset, ports 3 and 4, txd/p2.0, and rxd (in serial mode 0). the v oh specification is not valid for reset. ports 3 and 4 are open-drain outputs. 3. standard inputs include hsi pins, ready, buswidth, rxd/p2.1, extint/p2.2, t2clk/p2.3, and t2rst/p2.4. 4. maximum current per pin must be externally limited to the following values if v ol is held above 0.45v or v oh is held below v cc b 0.7v: i ol on output pins: 10 ma i oh on quasi-bidirectional pins: self limiting i oh on standard output pins: 10 ma 5. maximum current per bus pin (data and control) during normal operation is g 3.2 ma. 6. during normal (non-transient) conditions the following total current limits apply: port 1, p2.6 i ol :29ma i oh is self limiting hso, p2.0, rxd, reset i ol :29ma i oh :26ma p2.5, p2.7, wr , bhe i ol :13ma i oh :11ma ad0 ad15 i ol :52ma i oh :52ma rd , ale, inst clkout i ol :13ma i oh :13ma 7. violating these specifications in reset may cause the part to enter test modes. 8
M87C196KC/m87c196kd i cc max e 3.88 c freq a 8.43 i idle max e 1.65 c freq a 2.2 271116 21 figure 5. i cc and i idle vs frequency ac characteristics for use over specified operating conditions. the system must meet these specifications to work with the M87C196KC/kd: symbol description min max units notes t avyv address valid to ready setup 2 t osc b 75 ns t llyv ale low to ready setup t osc b 75 ns t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0 t osc b 30 ns (note 1) t llyx ready hold after ale low t osc b 15 2 t osc b 40 ns (note 1) t avgv address valid to buswidth setup 2 t osc b 75 ns t llgv ale low to buswidth setup t osc b 65 ns t clgx buswidth hold after clkout low 0 ns t avdv address valid to input data valid 3 t osc b 55 ns (note 2) t rldv rd active to input data valid t osc b 26 ns (note 2) t cldv clkout low to input data valid t osc b 50 ns t rhdz end of rd to input data float t osc b 5ns t rxdx data hold after rd inactive 0 ns notes: 1. if max is exceeded, additional wait states will occur. 2. if wait states are used, add 2 t osc * n, where n e number of wait states. 3. test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 16 mhz. 9
M87C196KC/m87c196kd ac characteristics (continued) for user over specified operating conditions. the M87C196KC/kd will meet these specifications: symbol description min max units notes f xtal frequency on xtal1 3.5 16 mhz kc/kd-16 3.5 20 mhz kd-20 t osc 1/f xtal 62.5 286 ns kc/kd-16 50 286 ns kd-20 t xhch xtal1 high to clkout high or low 10 110 ns t clcl clkout cycle time 2 t osc ns t chcl clkout high period t osc b 10 t osc a 20 ns t cllh clkout falling edge to ale rising b 515ns t llch ale falling edge to clkout rising b 29 a 15 ns t lhlh ale cycle time 4 t osc ns (note 3) t lhll ale high period t osc b 10 t osc a 15 ns t avll address setup to ale falling edge t osc b 15 t llax address hold after ale falling edge t osc b 49 ns t llrl ale falling edge to rd falling edge t osc b 36 ns t rlcl rd low to clkout falling edge 0 30 ns t rlrh rd low period t osc b 5 ns (note 3) t rhlh rd rising edge to ale rising edge t osc t osc a 25 ns (note 1) t rlaz rd low to address float 15 ns kc-16 30 ns kd-16/20 t llwl ale falling edge to wr falling edge t osc b 10 ns t clwl clkout low to wr falling edge 0 25 ns t qvwh data stable to wr rising edge t osc b 23 t chwh clkout high to wr rising edge b 10 15 ns t wlwh wr low period t osc b 30 ns (note 3) t whqx data hold after wr rising edge t osc b 30 ns t whlh wr rising edge to ale rising edge t osc b 10 t osc a 15 ns (note 1) t whbx bhe , inst after wr rising edge t osc b 10 ns t whax ad8 15 hold after wr rising t osc b 50 ns (note 2) t rhbx bhe , inst after rd rising edge t osc b 10 ns t rhax ad8 15 hold after rd rising t osc b 25 ns (note 2) notes: 1. assuming back-to-back bus cycles. 2. 8-bit bus only. 3. if wait states are used, add 2 t osc * n, where n e number of wait states. 4. test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 16 mhz. 10
M87C196KC/m87c196kd 271116 22 figure 6. system bus timings 11
M87C196KC/m87c196kd 271116 23 figure 7. ready timings (one waitstate) 271116 24 figure 8. buswidth timings 12
M87C196KC/m87c196kd hold /hlda timings symbol description min max units notes t hvch hold setup 55 ns (note 1) t clhal clkout low to hlda low b 15 15 ns t clbrl clkout low to breq low b 15 15 ns t halaz hlda low to address float 10 ns t halbz hlda low to bhe , inst, rd ,wr weakly driven 15 ns t clhah clkout low to hlda high b 15 15 ns t clbrh clkout low to breq high b 15 15 ns t hahax hlda high to address no longer float b 15 ns t hahbv hlda high to bhe, inst, rd, wr valid b 10 ns t cllh clkout low to ale high b 515 ns note: 1. to guarantee recognition at next clock. dc specifications in hold min max units weak pullups on adv , rd, 50k 250k v cc e 5.5v, v in e 0.45v wr ,wr l, bhe weak pulldowns on 10k 50k v cc e 5.5v, v in e 2.4 ale, inst 271116 25 figure 9. hold /hlda timings 13
M87C196KC/m87c196kd external clock drive symbol parameter min max units notes 1/t xlxl oscillator frequency 3.5 16.0 mhz kc/kd-16 3.5 20.0 mhz kd-20 t xlxl oscillator frequency 62.5 286 ns kc/kd-16 50 286 kd-20 t xhxx high time 22 ns kc/kd-16 17 ns kd-20 t xlxx low time 22 ns kc/kd-16 17 ns kd-20 t xlxh rise time 10 ns t xhxl fall time 10 ns 271116 26 figure 10. external clock drive waveforms 271116 27 ac testing inputs are driven at 2.4v for a logic ``1'' and 0.45v for a logic ``0'' timing measurements are made at 2.0v for a logic ``1'' and 0.8v for a logic ``0''. 271116 28 for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs i ol /i oh e g 15 ma. figure 11. ac testing input, output waveforms figure 12. float waveforms explanation of ac symbols each symbol is two pairs of letters prefixed by ``t'' for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. conditions: he high le low ve valid xe no longer valid ze floating signals: ae address be bhe ce clkout de data ge buswidth he hold hae hlda le ale/adv bre breq re rd we wr /wrh /wrl xe xtal1 ye ready qe data out 14
M87C196KC/m87c196kd ac characteristicseserial porteshift register mode serial port timingeshift register mode symbol parameter min max units t xlxl serial port clock period (brr t 8002h) 6 t osc ns t xlxh serial port clock falling edge 4 t osc g 50 ns to rising edge (brr t 8002h) t xlxl serial port clock period (brr e 8001h) 4 t osc ns t xlxh serial port clock falling edge 2 t osc g 50 ns to rising edge (brr e 8001h) t qvxh output data setup to clock rising edge 2 t osc b 50 ns t xhqx output data hold after clock rising edge 2 t osc b 50 ns t xhqv next output data valid after clock rising edge 2 t osc a 50 ns t dvxh input data setup to clock rising edge t osc a 50 ns t xhdx input data hold after clock rising edge 0 ns t xhqz last clock rising to output float 1 t osc ns waveformeserial porteshift register mode 271116 29 figure 13. serial port waveformeshift register mode thermal characteristics M87C196KC m87c196kd package i ja i jc i ja i jc type pga 29.5 c/w 6 c/w 29 c/w 4 c/w cqfp 30 c/w 9.5 c/w 30 c/w 11 c/w all thermal impedance data is approximate for static air conditions at 1w of power dissipation. values will change depending on operation conditions and application. see the intel packaging handbook (order number 240800) for a description of intel's thermal impedance test methodol- ogy. 15
M87C196KC/m87c196kd eprom specifications ac eprom programming characteristics operating conditions: load capacitance e 150 pf, t a ea 25 c g 5 c, v cc ,v ref e 5v, v ss , angnd e 0v, v pp e 12.50v g 0.25v, ea e 12.50v g 0.25v symbol description min max units t shll reset high to first pale low 1100 t osc t lllh pale pulse width 50 t osc t avll address setup time 0 t osc t llax address hold time 100 t osc t pldv prog low to word dump valid 50 t osc t phdx word dump data hold 50 t osc t dvpl data setup time 0 t osc t pldx data hold time 400 t osc t plph (2) prog pulse width 50 t osc t phll prog high to next pale low 220 t osc t lhpl pale high to prog low 220 t osc t phpl prog high to next prog low 220 t osc t phil prog high to ainc low 0 t osc t ilih ainc pulse width 240 t osc t ilvh pver hold after ainc low 50 t osc t ilpl ainc low to prog low 170 t osc t phvl prog high to pver valid 220 t osc notes: 1. run time programming is done with fosc e 6.0 mhz to 12.0 mhz, v ref e 5v g 0.50v. t a ea 25 cto g 5 c and v pp e 12.50v. 2. this specification is for the word dump mode. for programming pulses, use 300 t osc a 100 m s. dc eprom programming characteristics symbol description min max units i pp v pp supply current (when programming) 100 ma note: v pp must be within 1v of v cc while v cc k 4.5v. v pp must not have a low impedance path to ground of v ss while v cc l 4.5v. 16
M87C196KC/m87c196kd erasing the M87C196KC/kd eprom initially, and after each erasure, all bits of the M87C196KC/kd are in the ``1'' state. data is intro- duced by selectively programming ``0s'' into the de- sired bit locations. although only ``0s'' will be pro- grammed, both ``1s'' and ``0s'' can be present in the data word. the only way to change a ``0'' to a ``1'' is by ultraviolet light erasure. the erasure characteristics of the M87C196KC/kd are such that erasure begins to occur upon expo- sure to light with wavelengths shorter than approxi- mately 4000 angstroms ( e ). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000 4000 e range. constant exposure to room level fluorescent lighting could erase the typical M87C196KC/kd in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. if the M87C196KC/kd is to be exposed to light for extended periods of time, opaque labels must be placed over the eprom's window to prevent unin- tentional erasure. the recommended erasure procedure for the M87C196KC/kd is exposure to shortwave ultravio- let light which has a wavelength of 2537 e . the inte- grated dose (i.e., uv intensity c exposure time) for erasure should be a minimum of 15 wsec/cm 2 . the erasure time with this dosage is approximately 35 to 60 minutes using an ultraviolet lamp with a 12000 m w/cm 2 power rating. the M87C196KC/kd should be placed within 1 inch of the lamp tubes during erasure. the maximum integrated dose an M87C196KC/kd can be exposed to without dam- age is 7258 wsec/cm 2 (1 week @ 12000 m w/cm 2 ). exposure of the M87C196KC/kd to high intensity uv light for long periods may cause permanent dam- age. eprom programming waveforms 271116 30 figure 14. slave programming mode data program mode with single program pulse 17
M87C196KC/m87c196kd 271116 31 figure 15. slave programming mode in word dump with auto increment 271116 32 figure 16. slave programming mode timing in data program with repeated prog pulse and auto increment 18
M87C196KC/m87c196kd 10-bit a/d characteristics the speed of the a/d converter in the 10-bit mode can be adjusted by setting a clock prescaler on or off. at high frequencies more time is needed for the comparator to settle. the maximum frequency with the clock prescaler disabled is 6 mhz. the conver- sion times with the prescaler turned on or off is shown in the table below. the ad e time register has not been characterized for the 10-bit mode. the converter is ratiometric, so the absolute accura- cy is dependent on the accuracy and stability of v ref .v ref must be close to v cc since it supplies both the resistor ladder and the digital section of the converter. a/d converter specifications the specifications given below assume adherence to the operating conditions section of this data sheet. testing is performed with v ref e 5.12v. clock prescaler on clock prescaler off ioc2.4 e 0 ioc2.4 e 1 156.5 states 89.5 states 19.5 m s @ 16 mhz 29.8 m s @ 6 mhz parameter typical (3) minimum maximum units * notes resolution 1024 1024 levels 10 10 bits absolute error 0 g 8 lsbs full scale error g 3 lsbs zero offset error g 3 lsbs non-linearity 0 g 8 lsbs differential non-linearity error l b 1 a 2 lsbs channel-to-channel matching 0 g 1 lsbs repeatability g 0.25 lsbs temperature coefficients: offset 0.009 lsb/ c full scale 0.009 lsb/ c differential non-linearity 0.009 lsb/ c off isolation b 60 db 1, 2 feedthrough b 60 db 1 v cc power supply rejection b 60 db 1 input resistance 750 1.2k x dc input leakage 0 3.0 m a sample time: prescaler on 16 states prescaler off 8 states input capacitance 3 pf notes: * an ``lsb'', as used here, has a value of approximately 5 mv. 1. dc to 100 khz. 2. multiplexer break-before-make guaranteed. 3. typical values are expected for most devices at 25 c. 19
M87C196KC/m87c196kd 8-bit mode a/d characteristics the 8-bit mode trades off resolution for a faster con- version time. the ad e time register must be used when performing an 8-bit conversion. the following specifications are tested @ 16 mhz with oa6h in ad e time. sample time convert time 20 states 56 states a6h in ad e time 9.8 m s @ 16 mhz parameter typical minimum maximum units * notes resolution 256 256 levels 8 8 bits absolute error 0 g 2 lsbs full scale error g 1 lsbs zero offset error g 2 lsbs non-linearity 0 g 2 lsbs differential non-linearity error l b 1 a 1 lsbs channel-to-channel matching g 1 lsbs repeatability g 0.25 lsbs temperature coefficients: offset 0.003 lsb/ c full scale 0.003 lsb/ c differential non-linearity 0.003 lsb/ c notes: * an ``lsb'', as used here, has a value of approximately 20 mv. 1. typical values are expected for most devices at 25 c. 20
M87C196KC/m87c196kd M87C196KC design information M87C196KC enhanced feature set over the m80c196kb 1. the M87C196KC has twice the ram of the m80c196kb and 16 kbytes of eprom. also, a vertical register windowing scheme allows the extra 256 bytes of ram to be used as registers. this greatly reduces the context switching time. 2. peripheral transaction server (pts). the pts is an alternative way to service an interrupt, reducing latency and overhead. each interrupt can be mapped to its pts channel, which acts like a dma channel. each interrupt can now do a single or block transfer, without executing an interupt service routine. special pts modes exist for the a/d converter, hsi, and hso. 3. two extra pluse width modulated outputs. the M87C196KC has added 2 pwm outputs that are functional- ly compatible to the 80c196kb pwm. 4. timer2 internal clocking. timer2 can now be clocked with an internal source, every 1 or 8 state times. 5. the a/d can now perform an 8- as well as a 10-bit conversion. this trades off resolution for a faster conversion time. 6. additional on-chip memory security. two uprom (uneraseable programmable read only memory) bits can be programmed to disable the bus controller for external code and data fetches. once programmed, a uprom bit cannot be erased. by shutting off the bus controller for external fetches, no one can try and gain access to your code by executing from external memory. 7. new instructions. the M87C196KC has 5 new instructions. an exchange (xchb/xchw) instruction swaps two memory locations, an interruptable block move instruction (bmovi), a table indirect jump (tijmp) instruction, and two instructions for enabling and disabling the pts (epts/dpts). m80c196kb to M87C196KC design considerations 1. memory map. the M87C196KC has 512 bytes of ram/sfrs and 16k of eprom. the extra 256 bytes of ram will reside in locations 100h 1ffh and the extra 8k of eprom will reside in loca- tions 4000h 5fffh. these locations are exter- nal memory on the m80c196kb. 2. eprom programming. the M87C196KC has a different programming algorithm to support 16k of on-board memory. 3. once mode entry. the once mode is entered on the M87C196KC by driving the txd pin low on the rising edge of reset. the txd pin is held high by a pullup that is specified at 1.4 ma and remain at 2.0v. this pullup must not be overrid- den or the M87C196KC will enter the once mode. 4. during the bus hold state, the M87C196KC weakly holds rd, wr, ale, bhe and inst in their inactive states. the 80c196kb only holds ale in its inactive state. 5. a reset pulse from the M87C196KC is 16 states rather than 4 states as on the 80c196kb (i.e., a watchdog timer overflow). this provides a longer reset pulse for other devices in the sys- tem. 6. the cde pin on the kb has become a v ss pin on the kc to support 16 mhz operation. M87C196KC errata 1. missed extint on p0.7. the 80c196kc20 could possibly miss an extint on p0.7. see faxback y 2049. 2. his e mode divide-by-eight. see faxback y 2192. 3. ipd hump. see faxback y 2311. 21
M87C196KC/m87c196kd m87c196kd design information m87c196kd enhancements over the M87C196KC the m87c196kd is an enhanced, pin-for-pin compatible upgrade to the M87C196KC. the m87c196kd offers the same functionality, packages, and pin-outs as the M87C196KC with twice the on-chip eprom and register ram. 1. doubling the on-chip eprom to 32 kbytes allows for larger on-chip programs. 2. doubling the on-chip ram to 1000 bytes allows for faster and more optimized code execution. M87C196KC to m87c196kd design considerations due to the added memory, a few memory-specific functions have been modified on the m87c196kd. 1. the ac characteristic rd low to address float (t rlaz ) maximum has been increased from 15 ns on the M87C196KC to 30 ns on the m87c196kd. 2. the memory map is expanded to accommodate the additional memory. because the added mem- ory resides in memory locations that were always external to the M87C196KC, M87C196KC code may have to be modified to run on the m87c196kd. 3. the vertical windowing map is extended to allow all 1000 bytes of register ram to be windowed into the lower register file. 4. the m87c196kd has a different autoprogram- ming algorithm to support 32 kbytes of on-chip eprom. 22
M87C196KC/m87c196kd new M87C196KC/kd feature a clkout disable bit has been added to the ioc3 sfr. this can be used to reduce noise in systems that do not require the clkout signal. figure 17 indicates the placement of the new bit. 271116 34 note: * rsvereserved bits must be e 0 figure 17. m87c196kd new sfr bit (clkout disable) datasheet revision history the changes made since the october 1992 revision of the M87C196KC datasheet (271116-004) are as follows: 1. added m87c196kd information. 2. deleted the memory map figure. * 3. deleted the horizontal windowing figure. * 4. deleted the sfr bit summaries. * 5. added the new clkout disable feature. 6. modified the v ih2 and i cc dc specifications. 7. modified the t llyv ,t llgv ,t rldv ,t rhdz , t llch ,t lhll ,t llax ,t llrl ,t rlaz , and t whqx ac specifications. 8. modified the t halbz and t hahax hold/hlda specifications. 9. added the package thermal characteristics. * see the 87c196kc/kd user's manual (order y 272238) for this information. 23

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